Lavori attuali relativi a Design Verification Engineer SoC - Roma - Fondazione Chips-IT
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Principal Functional Verification Engineer
2 settimane fa
Roma, Italia microTECH Global LTD A tempo pienoAbout the Role: We are seeking a Principal Verification Engineer to lead functional verification for complex SoC/IP architectures. You will collaborate across architecture, design, physical implementation, and software teams, driving verification methodology, execution, and closure. Key Responsibilities: - Analyse system and architecture specifications to...
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Principal Functional Verification Engineer
4 settimane fa
Roma, Italia microTECH Global LTD A tempo pienoAbout the Role: We are seeking a Principal Verification Engineer to lead functional verification for complex SoC/IP architectures. You will collaborate across architecture, design, physical implementation, and software teams, driving verification methodology, execution, and closure. Key Responsibilities: - Analyse system and architecture specifications to...
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Principal Functional Verification Engineer
3 settimane fa
Roma, Italia microTECH Global LTD A tempo pienoAbout the Role We are seeking a Principal Verification Engineer to lead functional verification for complex SoC / IP architectures. You will collaborate across architecture, design, physical implementation, and software teams, driving verification methodology, execution, and closure. Key Responsibilities Analyse system and architecture specifications to...
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Principal Functional Verification Engineer
4 settimane fa
Giuliano di Roma, Italia microTECH Global LTD A tempo pienoAbout the Role:We are seeking a Principal Verification Engineer to lead functional verification for complex SoC/IP architectures. You will collaborate across architecture, design, physical implementation, and software teams, driving verification methodology, execution, and closure. Key Responsibilities: • Analyse system and architecture specifications to...
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Principal Functional Verification Engineer
1 settimana fa
Giuliano di Roma, Italia microTECH Global LTD A tempo pienoAbout the Role We are seeking a Principal Verification Engineer to lead functional verification for complex SoC / IP architectures. You will collaborate across architecture, design, physical implementation, and software teams, driving verification methodology, execution, and closure. Key ResponsibilitiesAnalyse system and architecture specifications to...
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Principal Functional Verification Engineer
1 settimana fa
Roma, Lazio, Italia microTECH Global LTD A tempo pieno 80.000 € - 120.000 € all'anoAbout the Role:We are seeking a Principal Verification Engineer to lead functional verification for complex SoC/IP architectures. You will collaborate across architecture, design, physical implementation, and software teams, driving verification methodology, execution, and closure.Key Responsibilities:• Analyse system and architecture specifications to...
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Lead SoC Verification Architect | SystemVerilog, UVM, C++
3 settimane fa
Roma, Italia microTECH Global LTD A tempo pienoA leading technology company in Italy is seeking a Principal Verification Engineer to lead functional verification for complex SoC/IP architectures. The role involves collaboration across various teams and extensive debugging experience. Ideal candidates will have a Master's degree and over 15 years of verification expertise with strong SystemVerilog and UVM...
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Lead SoC Verification Architect | SystemVerilog, UVM, C++
3 settimane fa
Roma, Italia microTECH Global LTD A tempo pienoA leading technology company in Italy is seeking a Principal Verification Engineer to lead functional verification for complex SoC/IP architectures. The role involves collaboration across various teams and extensive debugging experience. Ideal candidates will have a Master’s degree and over 15 years of verification expertise with strong SystemVerilog and...
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Senior Formal Verification Engineer
3 settimane fa
Roma, Italia Openchip & Software Technologies A tempo pienoAs a Senior Formal Verification Engineer, you will contribute to defining and leading the formal verification strategy for our systems. Responsibilities Work closely with system architects and design team to establish formal verification environment and setting Guide the use of formal verification that correct formal techniques are used appropriately to...
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Senior Formal Verification Engineer
3 settimane fa
Roma, Italia Openchip & Software Technologies A tempo pienoAs a Senior Formal Verification Engineer, you will contribute to defining and leading the formal verification strategy for our systems. Responsibilities - Work closely with system architects and design team to establish formal verification environment and setting - Guide the use of formal verification that correct formal techniques are used appropriately to...
Design Verification Engineer SoC
4 settimane fa
Role The Chips-IT Foundation is seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System-on-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry-standard methodologies (e.g., UVM), ensuring functional correctness of designs from specification to tape-out. The position also involves collaboration with design, architecture, and software teams to deliver reliable and high-quality silicon. The work can be carried out either in Pavia or in Bologna. Key Responsibilities: Define and implement verification strategies at IP and SoC levels. Develop and maintain UVM-based verification environments, including testbenches and functional coverage. Design and execute test plans aligned with design specifications and requirements. Debug RTL and simulation issues using advanced tools and techniques. Integrate verification components and ensure complete test coverage. Contribute to regression infrastructure and manage automated test execution. Collaborate closely with RTL designers, DFT engineers, and physical implementation teams. Support post-silicon bring-up and validation activities as needed. Required Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field. At least 5 years of experience in digital design verification. Strong knowledge of SystemVerilog and UVM methodology. Hands-on experience with simulation and debug tools (e.g., QuestaSim, VCS, Verdi). Familiarity with industry-standard protocols such as AMBA AXI, APB, and AHB. Experience in writing constrained-random testbenches and analyzing coverage metrics. Good understanding of digital design, SoC architecture, and RTL development. Strong teamwork, communication, and documentation skills. What we offer Competitive compensation and contract type, to be negotiated based on qualifications and experience Lunch tickets Private health care coverage depending on your role and contract Structured growth path, with ongoing access to training and updates Networking opportunities with industry-leading professionals International environment Hybrid work policy Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years About Fondazione Chips-IT The Foundation "Italian Center for the Design of Semiconductor Integrated Circuits," also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry. The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise. Missions of the Foundation: promote the design and development of integrated circuits strengthen the system of professional training in the field of microelectronics ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field Disclaimer No ranking list or list of suitable candidates will be prepared and published. The Foundation reserves the right to: a. extend or reopen the deadline of this notice; b. revoke this notice; c. not make any selection from among the applications submitted if they are deemed not to meet the functions set forth in the notice; without any claims or rights being asserted by the interested parties. Non verrà redatta e pubblicata alcuna graduatoria o elenco degli idonei. La Fondazione si riserva la facoltà di: a. prorogare o riaprire il termine di scadenza del presente avviso; b. revocare il presente avviso; c. non procedere ad alcuna scelta tra le candidature presentate, ove ritenute non rispondenti alle funzioni di cui all'avviso; senza che gli interessati possano avanzare alcuna pretesa o diritto.
