Senior Digital Design And Risc-V Architecture Engineer

Role The Chips-IT Foundation is seeking Senior Researchers to lead and contribute to cutting‑edge research and development initiatives centered on digital design and RISC‑V architectures. The project focuses on the development of advanced digital processors, accelerators, and custom SoCs based on the RISC‑V instruction set architecture (ISA), as well as domain‑specific hardware accelerators. This role will involve leading the design, optimization, and verification of high‑performance, low‑power digital systems for next‑generation computing platforms, IoT, and embedded applications. Senior Researchers will play a key role in defining design methodologies, driving innovation in hardware‑software co‑design, and contributing to the advancement of the RISC‑V ecosystem at both technical and strategic levels. The work can be carried out either in Pavia or in Bologna. Key Responsibilities Lead research and development activities in digital design, including processors, accelerators, and SoCs based on RISC‑V architecture. Define and guide the architecture, design, implementation, and verification of complex digital subsystems (Processors, Accelerators, Memory and Communication Subsystems, etc.). Supervise and mentor junior researchers, including Master’s and PhD students, across multiple research and development projects. Develop and disseminate research outcomes through publications in high‑impact scientific journals and presentations at leading international conferences. Drive the adoption of emerging methodologies in digital design, verification, and hardware‑software co‑design. Collaborate with industry and academic partners, contributing technical leadership and vision to multi‑stakeholder projects. Support the development of project proposals and strategic R&D initiatives aligned with national and international funding opportunities. Required Qualifications Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field with a strong focus on digital design and processor architectures. At least 10 years of experience in digital hardware design, preferably with a mix of academic and industrial exposure. Deep proficiency in hardware description languages (Verilog, VHDL) and digital design toolchains for synthesis, simulation, and verification. Extensive experience with RISC‑V architecture, including custom ISA extensions, microarchitecture design, and hardware‑software co‑design. Hands‑on experience with tape‑outs and chip bring‑up in advanced CMOS / FinFET technology nodes (28nm, 16nm, or below). Proven knowledge in FPGA / ASIC design flows, integration of complex SoCs, and system‑level verification. What We Offer Competitive compensation and contract type, to be negotiated based on qualifications and experience. Lunch tickets. Private health care coverage depending on your role and contract. Structured growth path, with ongoing access to training and updates. Networking opportunities with industry‑leading professionals. International environment. Hybrid work policy. Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years. About Fondazione Chips‑IT The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips‑IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry. The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise. Missions of the Foundation Promote the design and development of integrated circuits; strengthen the system of professional training in the field of microelectronics; ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field. Disclaimer No ranking list or list of suitable candidates will be prepared and published. The Foundation reserves the right to: a) extend or reopen the deadline of this notice; b) revoke this notice; c) not make any selection from among the applications submitted if they are deemed not to meet the functions set forth in the notice; without any claims or rights being asserted by the interested parties. Non verrà redatta e pubblicata alcuna graduatoria o elenco degli idonei. La Fondazione si riserva la facoltà di: a) prorogare o riaprire il termine di scadenza del presente avviso; b) revocare il presente avviso; c) non procedere ad alcuna scelta tra le candidature presentate, ove ritenute non rispondenti alle funzioni di cui all’avviso; senza che gli interessati possano avanzare alcuna pretesa o diritto. #J-18808-Ljbffr