Senior DV Engineer: SoC, UVM

4 settimane fa


Milan, Italia Vendita al dettaglio e all'ingrosso Import-export A tempo pieno

A global leader in technology is seeking a Senior Design Verification Engineer in Milano, Italy. In this role, you will enhance hardware designs and implement verification methodologies for advanced functional blocks. The ideal candidate should have over 10 years of ASIC experience and proficiency in SystemVerilog and UVM. Join a culture that empowers innovation and delivers results for customers.#J-18808-Ljbffr



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