ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

5 giorni fa


pisa, Italia Amazon A tempo pieno

ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration teamAnnapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.About AWS: Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.This role is based in Tel Aviv with an option for relocation to the USA (not a must).Key job responsibilitiesIntegrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routingAs a key member of the ASIC design team, implement and deliver high performance, area and power efficient RTL to achieve design targets and specificationsAnalyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirementsDevelop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraintsPerform lint and clock domain crossing quality checks on the designWork with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasksYou will thrive in this role if youAre familiar with scripting in PythonAre proficient with assertionsHave good debug skills to analyze RTL test failuresHave a \"Learn and Be Curious\" mindsetAbout the teamCustom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world‑class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Engineer to help us trail‑blaze new technologies and architectures, while ensuring high design quality and making the right trade‑offs.Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge‑sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.Basic Qualifications3+ years in RTL design for SOC3+ years of VLSI engineering3+ years with code quality tools including: Spyglass, LINT, or CDCPreferred QualificationsExperience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraintsFamiliarity with data path design, interconnects, AXI protocolGood analytical, problem solving, and communication skillsOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability or other legally protected status.#J-18808-Ljbffr



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    A leading cloud computing company is seeking an ASIC Design Engineer for their Cloud‑Scale Machine Learning Acceleration team in Pisa, Italy. The ideal candidate will design and optimize hardware, focusing on SOC integration, and ensure high-quality deliverables. Candidates should possess extensive experience in RTL design, VLSI engineering, and code...


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