Design Verification Engineer

1 settimana fa

Roma, Lazio, Italia Yo It Group A tempo pieno

20,00USD/hr - 40,00USD/ora Position:Design Verification Engineer - VLSI/ASIC/FPGA Hardware Experience:3 - 25 Years Location:Permanent Remote anywhere in the World Contract Length:6 Months Type:Full time contract (8 hrs/day) Overlap Hours: 4 hrs/day with PST Mandatory Skills: Overall - 5 years of experience.
Minimum of 2 years of relevant experience in Hardware Design and/or Hardware Verification.
Experience with one or more of the following: ASIC VLSI FPGA SOC Experience with one or more of the following: SystemVerilog development Verilog development Testbench development and/or verification.
Good communication skills in English.
LLM experience is not mandatory; however, the candidate should be willing to work as an LLM Engineer for Verilog.
Must-Have: BS or MS degree in Electrical Engineering or related field.
3-5 years of proven experience in hardware design development.
Expertise in HDLs such as Verilog, SystemVerilog, VHDL, and SystemC.
Expertise in scripting, front-end and verification workflows, and integrations within the hardware design environment.
Expertise in UVM environments.
Expertise in Formal Verification.
Expertise in Lint process and refinement.
Good communication skills in English.
Job Description:We're searching for an exceptional hardware design Developer to play a pivotal role in using the hardware design platform to generate the training data to enhance enterprise LLMs' capabilities.
This unique position offers the chance to directly contribute to the sophistication of enterprise LLMs, ensuring they operate with unparalleled efficiency and intelligence.
Your Mission: Develop, configure, and customize the hardware design platform, utilizing it to generate vital training data for enterprise LLMs.
Liaise with research teams to translate requirements into actionable data insights, directly impacting our LLMs' performance.
Uphold the highest standards in coding, debugging, and documentation, ensuring the hardware design solutions are optimized for LLM training and benchmarking.
Collaborate across teams to identify and prioritize needs, contributing to the LLMs' ability to understand and automate complex processes.
We Need: BS or MS degree in Electrical Engineering or related field.
3-5 years of proven experience in hardware design development.
Expertise in HDLs such as Verilog, SystemVerilog, VHDL, and SystemC.
Expertise in scripting, front-end and verification workflows, and integrations within the hardware design environment.
Exceptional problem-solving, communication, and collaborative skills.
Familiarity with ML and AI systems.
Skills:front-end, integrations in hardware design, testbench development, ML and AI systems, SystemC, integrations within the hardware design environment, hardware design, Verilog development, VHDL, communication, formal verification, front-end verification workflows, integrations within hardware design environment, hardware verification, communication skills, universal verification methodology (UVM), problem-solving, Lint process, coding, UVM, knowledge of ML and AI systems, integration, HDLs (Verilog, SystemVerilog, VHDL, SystemC), HDLs, HDL, design, FPGA, integrations, front-end development, verification, communication skills in English, UVM environments, scripting, debugging, electrical engineering, Lint process refinement, HDL expertise, AI systems, documentation, Verilog, HDLs (VHDL, SystemC), SystemVerilog, integration within hardware design environment, SOC, SystemVerilog development, collaborative skills, VLSI, hardware design development, front-end and verification workflows, ML and AI familiarity, Verilog-A, front-end workflows, ASIC, electronics hardware design, good communication skills, collaboration, machine learning, AI, AI and ML familiarity, Lint process and refinement, ML, verification workflows, familiarity with ML and AI systems.#J-18808-Ljbffr

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