Senior ASIC Physical Design Engineer

1 mese fa


Agrate Brianza, Lombardia, Italia Synopsys A tempo pieno
Job Description

As a Senior ASIC Physical Design Engineer, you will be responsible for the physical implementation of complex IPs and test-chips across multiple process technologies with a focus on advanced high-speed SERDES platforms.

This role requires a strong understanding of the full design cycle from RTL to GDSII, including chip-level implementation. You will work closely with multiple functional groups and the product team to drive all aspects of physical implementation, from RTL to GDS, including timing and physical sign-off.

The successful candidate will have:

  1. 10+ years of digital or physical design experience with recent contribution to project tape-outs, as a technical driver and/or project head.
  2. Intimate understanding of advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques.
  3. Development of timing constraints and design architectures to ensure on-time delivery, and to meet or exceed power and area targets.
  4. Excellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers.
  5. Solid understanding of the challenges inherent in analog/digital interfaces.

Requirements:

  1. MSEE and 8+ years or BSEE and 10+ years.
  2. Previous project leadership experience.
  3. Solid understanding of digital/mixed signal verification flows and SOC integration challenges.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk.



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