Lavori attuali relativi a SystemVerilog Verification Engineer - Modena, Emilia-Romagna - TN Italy
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Digital Verification Engineer
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Digital Verification Engineer
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Design Verification Engineer
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Digital Verification Engineer
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Digital Verification Engineer
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Modena, Emilia-Romagna, Italia Tn Italy A tempo pienoDigital Verification Engineer - ModenaThis is a superb opportunity for an IC Verification Engineer to join an award-winning electronics company based in Modena, Italy.Here the IC Verification Engineer will:Join a motivated, passionate IC design team working on a major low power ASIC microcontroller project.Be responsible for developing test plans, tests, and...
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Low Power ASIC Microcontroller Engineer
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Modena, Emilia-Romagna, Italia Ic Resources A tempo pienoAbout the RoleThe IC verification engineer will be responsible for developing test plans, tests, and the verification environment using SystemVerilog and UVM. The role also involves working on coverage-driven verification closure, formal verification, and gate-level simulations.
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UVM SystemVerilog Expert
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Digital IC Verification Specialist
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Modena, Emilia-Romagna, Italia Ic Resources A tempo pienoJob OverviewThis is a superb opportunity for an IC verification engineer to join a leading electronics company in Italy. The ideal candidate will have experience in digital IC verification and UVM environments.
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Design And Manufacturing Engineer
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Regulatory & Product Development Specialist - Biomedicale
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IMPIEGATO BACK OFFICE
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SystemVerilog Verification Engineer
2 settimane fa
**Why Join Us?**
TN Italy offers a collaborative and dynamic work environment that fosters growth and innovation. Our team members enjoy a competitive salary package, flexible working hours, and a pleasant office location. As an IC Verification Engineer, you will have the opportunity to work on challenging projects, develop your skills, and contribute to the success of our company.
We are seeking a talented individual who can bring their expertise in Digital IC Verification to our team. The successful candidate will be responsible for developing test plans, tests, and the verification environment using SystemVerilog and UVM. They will also be involved in coverage-driven verification closure, formal verification, and gate-level simulations. Additionally, they will have the chance to coach junior verification engineers and participate in the full development process, from architecture decisions to mass production.
A Bachelor's degree in Electronics Engineering or a related field is required. Experience in digital RTL design is desirable but not necessary. We value candidates who are proactive, enthusiastic, and committed to delivering high-quality results.
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