Senior Analog Design Engineer

1 giorno fa


Pavia, Lombardia, Italia Synopsys A tempo pieno

We're seeking a seasoned Senior Analog Design Engineer to join our team in developing high-speed analog integrated circuits.

Main Responsibilities:

  • Investigate and develop circuit architectures that address architectural bottlenecks, driving improvements in power, area, and performance targets.
  • Oversee physical layout to minimize the effects of parasitics, device stress, and process variation.
  • Document design features and test plans.
  • Consult on the overall electrical characterization of the SerDes IP product, investigating customer silicon data for design enhancements and proposing solutions for post-silicon design updates.

Key Requirements:

  • PhD or MSc with 2+ years of practical analog IC design experience, degree in Electrical Engineering or similar.
  • Deep knowledge of transistor-level circuit design, with a focus on high-speed analog design.
  • Design experience with at least one sub-circuit relevant to SerDes: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC.

The ideal candidate will have expertise in layout effects (matching, reliability, proximity effects) and knowledge of Verilog-A for analog behavioral modeling. Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is a plus.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Estimated Salary Range: $120,000 - $180,000 per annum, depending on location and experience.



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