Verification Engineer

4 settimane fa


Milano, Lombardia, Italia Onsemi A tempo pieno

Onsemi's Power Management Division is seeking a skilled verification engineer to join their team. The ideal candidate will have experience in block/top level verification of integrated circuits using Verilog and UVM, as well as excellent teamwork skills.

The successful candidate will be responsible for creating block level verification test plans based on the specification of power management integrated circuits, building and maintaining verification environments, and driving quality to achieve maximum target of code and functional coverage.

Additionally, the candidate will develop regression suites to satisfy coverage targets, be responsible for analyzing and debugging failures, and drive innovation in verification technology.

The ideal candidate will have a strong background in digital verification, with experience in scripting languages such as TCL, CSH, and Python. They will also have experience in assertion-based verification, including PSL and SVA, and be familiar with industry-standard EDA tools.

As a member of the Onsemi team, the successful candidate will have the opportunity to work in a diverse, inclusive, and socially responsible environment. They will be part of a global team and will be responsible for guaranteeing the completion of assigned tasks on time.

Responsibilities:

  • Create block level verification test plans based on specification of power management integrated circuits
  • Build and maintain verification environment
  • Drive the quality to achieve maximum target of code and functional coverage
  • Develop regression suite to satisfy coverage targets
  • Be responsible for analyzing and debugging the failures
  • Drive innovation in verification technology
  • Write documentation and user guides for team members
  • Provide written and oral communication with the development team regarding coverage reviews, code reviews, deliverables, project updates and issues
  • BSEE/MSEE or equivalent required with a minimum of 5 years of experience
  • Solid knowledge of UVM and familiarity with vertical reuse techniques
  • Familiar to use of industry standard EDA tools
  • Strong experience in debugging
  • In depth knowledge and several years of proven experience in digital verification
  • Hand-on experience with Verilog, System Verilog, Verilog AMS, and UVM
  • Experience in scripting: TCL, CSH, python
  • Experience in Assertion Based Verification: PSL and SVA
  • Experience in debugging simulation failures
  • Passionate, self-driven and able to work with remote teams
  • Experience with formal methodology for functional coverage is a plus
  • Multi phase switching regulators a plus experience is a plus
  • Excellent verbal and written communication skills


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