Layout Engineering

At OpenChip, we are building the future of hardware. Our mission is to revolutionize semiconductor design through open-source principles, collaboration, and radical innovation. We develop high-performance Systems-on-Chip (SoCs) that power tomorrow's technologies. Our team is made up of brilliant, creative, and passionate people, and we are looking for a talented Physical Layout Engineer to join our adventure. The Role: As a Physical Layout Engineer, you will be a cornerstone of our design team, responsible for crafting the high-level physical architecture of our complex SoCs. You will translate complex digital architectures into efficient and robust floorplans, ready for implementation. You will work closely with the design teams to ensure our chips meet the highest standards of performance, power, and area (PPA). This is a unique opportunity to make your mark on cutting-edge projects in a dynamic and collaborative environment. Responsibilities: · Develop and own the top-level floorplan for complex SoCs, from early-stage planning to final implementation handoff. · Utilize Cadence Virtuoso to perform block placement, macro integration (SRAMs, analog IP), and chip-level assembly. · Manage the third-party IPs, taking care of the retrieval and storage. · Design, implement, and analyze the chip's power delivery network (PDN) to ensure electrical and performance robustness. · Work closely with analog and digital design teams to ensure the seamless integration of custom blocks and IPs at the chip level. · Perform early-stage routing feasibility studies, I/O ring planning, and critical pin assignments. · Run top-level physical verification (DRC, LVS, ERC) using industry-standard tools to ensure the floorplan is clean and manufacturable. · Develop and maintain WSP for custom layout integration. · Develop and maintain automation scripts (using SKILL, Tcl, or Python) to improve floorplanning efficiency and flow predictability. Qualifications: Core Requirements: · Technical diploma or Relevant experience in the field. · 5+ years of direct experience in physical layout or physical design, with a strong focus on chip-level floorplanning. · Expert-level proficiency with Cadence Virtuoso for custom layout and top-level chip assembly. · Practical experience with physical verification tools (e.g., Siemens/Mentor Calibre). · A solid understanding of power grid design principles and IR drop analysis. · Strong scripting skills in SKILL, Tcl, or Python. · Meticulous attention to detail and excellent problem-solving abilities. Preferred Qualifications: · Experience with advanced technology nodes (e.g., 7nm/5nm FinFET). · Familiarity with mixed-signal or custom-digital design flows. · Knowledge of low-power design methodologies (UPF). · Familiarity with the open-source hardware ecosystem (e.g., RISC-V). What We Offer? · A highly competitive salary and benefits package. · A flexible, collaborative, and results-oriented work environment. · The opportunity to work on revolutionary projects with a global impact. · A dedicated budget for training and professional growth. · The chance to actively contribute to a fast-growing company. . The position is based both Italy in Spain. We are looking for outstanding people willing to join our mission to change this industry and help to build a better world. If you feel identified with Openchip, please contact us. We can offer a competitive compensation package in a flexible work schema that will help you to keep a balance between your personal and professional life. At Openchip & Software Technologies S.L. , we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.