Senior/staff Circuit Designer
3 giorni fa
Hardware Engineer - Circuit Design (Italy based)
Join to apply for the Hardware Engineer - Circuit Design (Italy based) role at Axelera AI
About Us
Axelera AI is not your regular deep-tech startup.
We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.
In just four years, we have raised a total of $120 million and have built a world-class team of 220+ employees (including 49+ Ph Ds with more than 40,000 citations), both remotely from 17 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.
We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.
Our unwavering commitment to innovation has firmly established us as a global industry pioneer.
Are you up for the challenge?
Position Overview
We are seeking a Senior/Staff Circuit Designer to play a critical role in the electronic design and development of advanced AI accelerators products, such as cards and board computer, with a focus on ARM and x86-based architectures.
This role requires a visionary leader with deep technical expertise to drive innovation, provide strategic technical leadership, and mentor team members while executing hands‑on design responsibilities.
As a Staff Circuit Designer, you will contribute directly to defining and realizing cutting‑edge solutions that are central to our product portfolio.
Key Responsibilities
System Architecture: Lead architecture definition for products using Axelera AI accelerators and ARM/x86 compute boards.
Drive tech decisions for competitive differentiation.
Schematic Design: Convert architectures into detailed schematics; guide teams and suppliers to deliver reliable, standards‑compliant designs.
Advanced Board Design: Collaborate with Silicon, Layout, Mechanical, Thermal, and Validation teams to optimize high‑speed digital designs (LPDDR4+, PCIe 3.0+) and demanding PDNs (
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