Senior Digital Verification engineer

22 ore fa

Napoli, Campania, Italia JobLeads Tempo pieno

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# Senior Digital Verification engineerNapoli, ItalyID: 11154---## Job description

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*LA NOSTRA STORIA
**Noi di ST crediamo nel potere della tecnologia di guidare l’innovazione e avere un impatto positivo sulle persone, sulle imprese e sulla società.

Siamo un'azienda globale di semiconduttori e la nostra tecnologia avanzata e i nostri chip costituiscono la parte nascosta del mondo in cui viviamo oggi.
**Entrando in ST farai parte di un'azienda di oltre 115 nazionalità e presente in 40 paesi, con oltre 50.000 creatori di tecnologia in tutto il mondo
**Lo sviluppo di tecnologie richiede più del solo talento: siamo infatti alla ricerca di persone straordinarie che comprendano la collaborazione e il rispetto.

Persone con passione e il desiderio di rompere lo status quo, guidare l'innovazione e sbloccare il proprio potenziale.

Intraprendi un viaggio con noi, dove puoi innovare per un futuro che vogliamo rendere più intelligente e più verde, in modo responsabile e sostenibile.

La nostra tecnologia inizia con te..
*Role
We are looking for a
Digital Verification Engineer – SoC
to join our
MDRF-RFOC-DVCC
Digital Verification team in
Naples
, dedicated to the digital verification of complex
SoC/IP
for
automotive / industrial
applications.The selected candidate will work on
SystemVerilog UVM testbenches
,
firmware / drivers in C
, and
Python scripts
for automation, contributing to the entire verification cycle: from strategy definition to environment creation, up to coverage analysis and debug.

Within the team we also use
AI-assisted tools and methodologies
to accelerate development, debug, and results analysis, and we expect the candidate to be curious and interested in leveraging these technologies in day-to-day activities.
Main Responsibilities
* Define, in collaboration with architects and designers, the
verification strategy
at IP and/or SoC level.
* Develop and maintain
UVM testbenches in SystemVerilog
(environment, agent, sequencer, driver, monitor, scoreboard).
* Write and integrate
C tests
for subsystem and SoC verification in simulation and/or emulation environments.
* Develop
Python scripts
(and, when needed, bash/Tcl/Perl) for: + regression automation, + post-processing of results, + coverage analysis and report generation.
* Perform
functional debug
of failing test cases, interacting with the design (RTL) team and system architects.
* Run and debug gate-level simulations with SDF back-annotation
, analyzing timing-related issues and collaborating with design and implementation teams to identify and resolve problems.
* Analyze and manage
functional coverage
and
code coverage
, proposing new tests or testbench improvements to meet quality targets.
* Use
AI-assisted tools and workflows
for: + generation and review of testbench code and scripts, + log analysis, + debug acceleration.
* Contribute to the
continuous improvement of verification flows
(methodologies, common libraries, guidelines, best practices).
* Produce clear and structured documentation for: + verification specifications, + testbench architecture, + test plans, + key results.
Technical Requirements
Mandatory (must-have)
* Degree in
Electronic Engineering
,
Computer Engineering/Science
,
Physics with an electronics focus
, or related disciplines.
* Solid knowledge of
digital verification of integrated circuits
(RTL concepts, testbench, stimuli, checkers, coverage).
* Hands-on experience with
SystemVerilog
and
UVM methodology
: + development of UVM components (sequencer, driver, monitor, scoreboard), + environment configuration, + sequence and virtual sequence management.
* Good command of the
C language
for verification-oriented test/firmware driver development.
* Experience with
Python
for scripting and automation.
* Good knowledge and practical use of the
Unix/Linux environment
(shell, file system, batch jobs, compilation, basic scripting).
* Familiarity with major
digital simulators
(e.g.
Cadence Xcelium, Synopsys VCS, Siemens Questa
).
* Basic knowledge of
version control flows
(
Git, SVN, DesignSync
).
* Good command of
written and spoken English
.
* 5-8 years of experience in the role
Desirable (nice-to-have)
* Experience with
SoC/IP verification
(AMBA/AXI/APB/AHB buses, memory interfaces, peripherals, interrupt controllers, DMA, etc.).
* Basic

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