Senior Digital Design Engineer — RTL/Verilog, Bonus

1 giorno fa

Fiumefreddo Sicilia, Sicily, Italia Renesas Tempo pieno 37.000 € - 50.000 € Contratto

Renesas in Catania is seeking a Senior Digital Design Engineer to contribute to next-generation power management solutions for AI, Cloud and Data Center applications.

Si assicuri di leggere l'intera descrizione riportata di seguito e di candidarsi immediatamente se è sicuro/a di soddisfare tutti i requisiti.

You will design digital blocks in Verilog/SystemVerilog and work with cross-functional teams to deliver robust RTL.

The role offers a yearly salary range of €37,000 to €50,000 with potential xbvzest bonus; based in Catania, it requires good English communication and a collaborative mindset.