Hybrid ASIC Physical Design Engineer

In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You’ll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP...

NXP's Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP's advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous...

In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You’ll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP...

Nokia in Italy seeks a SoC Physical Design Engineer in Catania to advance PD for Optical Network ASICs across 3/5/7nm nodes. You will floorplan, place and route, and manage power/clock distribution, while driving RTL-to-GDSII flows.You will verify timing at block and chip level, collaborate with logic designers, and develop PD methodologies with automation...

Nokia in Italy seeks a SoC Physical Design Engineer in Catania to advance PD for Optical Network ASICs across 3/5/7nm nodes.Il suo CV è pronto? Se sì, e se è convinto/a che questo sia il ruolo giusto per lei, si candidi il prima possibile.You will floorplan, place and route, and manage power/clock distribution, while driving RTL-to-GDSII flows.You will...

Nokia in Italy seeks a SoC Physical Design Engineer in Catania to advance PD for Optical Network ASICs across 3/5/7nm nodes. You will floorplan, place and route, and manage power/clock distribution, while driving RTL-to-GDSII flows.You will verify timing at block and chip level, collaborate with logic designers, and develop PD methodologies with automation...

NXP Semiconductors in Italy is seeking an experienced Senior Physical Design Engineer to contribute to the physical design and implementation of complex, high‑performance semiconductor ICs, focusing on timing closure, floorplanning, place and route, and power integrity. xbvzest Per candidarsi, è sufficiente leggere la seguente descrizione del lavoro e...

In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You’ll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP...

Nokia in Italy seeks a SoC Physical Design Engineer in Catania to advance PD for Optical Network ASICs across 3/5/7nm nodes. You will floorplan, place and route, and manage power/clock distribution, while driving RTL-to-GDSII flows.You will verify timing at block and chip level, collaborate with logic designers, and develop PD methodologies with automation...