SoC Physical Design Engineer: Power, Timing

Nokia in Italy is seeking an experienced SoC Physical Design Engineer to drive physical design for Optical Network ASICs across 3/5/7nm nodes, focusing on power, performance, and area. You will perform floorplanning, place & route, and timing closure, collaborate with logic designers and hardware teams, and develop PD methodologies and automation scripts...

Nokia in Italy is seeking an experienced SoC Physical Design Engineer to drive physical design for Optical Network ASICs across 3/5/7nm nodes, focusing on power, performance, and area. You will perform floorplanning, place & route, and timing closure, collaborate with logic designers and hardware teams, and develop PD methodologies and automation scripts...

Nokia in Italy is seeking an experienced SoC Physical Design Engineer to drive physical design for Optical Network ASICs across 3/5/7nm nodes, focusing on power, performance, and area. You will perform floorplanning, place & route, and timing closure, collaborate with logic designers and hardware teams, and develop PD methodologies and automation...

Nokia in Italy is seeking an experienced SoC Physical Design Engineer to drive physical design for Optical Network ASICs across 3/5/7nm nodes, focusing on power, performance, and area. You will perform floorplanning, place & route, and timing closure, collaborate with logic designers and hardware teams, and develop PD methodologies and automation scripts...

In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You’ll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP...

In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You'll tackle floorplanning, placement, routing, and timing closure, shaping multi-project...

In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You'll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP and...

In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You’ll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP...

About HuaweiVerifichi che le sue competenze e la sua esperienza corrispondano ai requisiti di questo ruolo, quindi si candidi con il suo CV qui sotto.Huawei is a leading global provider of information and communications technology (ICT) infrastructure and smart devices. With integrated solutions across four key domains – telecom networks, IT, smart...