Physical Design Manager Engineer

3 giorni fa

Roma, Lazio, Italia OPENCHIP & SOFTWARE TECHNOLOGIES A tempo pieno

The Role
As a
Physical Design Manager Engineer,
you will serve as the technical reference point for the most complex digital blocks (high-speed, mixed-signal control, or automotive low-power). You will operate at the intersection of logic and physics, ensuring that the functional design intent is preserved and optimized during physical implementation.

Key Responsibilities

  • Strategic Physical Implementation & Constraint Management
  • Drive the entire implementation flow (Floorplanning, P&R, Clock Tree Synthesis) with a "constraint-driven" approach.
  • Functional Context Analysis: Anticipate routing and timing bottlenecks .
  • Dynamic Constraint Management: Analyze, clean, and regenerate timing constraints at every stage (Pre-Placement, Placement, Pre-CTS, Post-CTS, Sign-off), ensuring they reflect both the physical reality of the silicon and the functional requirements (e.g., Multi-Cycle Paths, distinguishing real vs. spurious False Paths).
  • Timing Sign-off & ECO Leadership
  • Manage complex timing closures (Multi-clock domains, asynchronous interfaces) using advanced techniques (DMSA, OCV/AOCV/POCV).
  • Drive ECO (Engineering Change Order) strategies not just at the gate level, but by proposing changes when the physical impact requires it.
  • Oversee Signal Integrity (SI) and Power Integrity analysis.

Requirements (Must Have)

  • Experience: 10+ years in the semiconductor industry with a focus on Physical Design and Digital Implementation.
  • Constraint Mastery: Expert knowledge of the SDC format and the ability to write and debug complex constraints for multi-mode/multi-corner (MMMC) designs.
  • Timing Closure: Solid experience in STA (PrimeTime/Tempus), CDC (Clock Domain Crossing) analysis, and managing hold/setup violations in advanced technology nodes or critical automotive contexts.
  • Scripting: Excellent automation skills (Tcl, Python, Perl) for report analysis and massive data flow management.

Preferred Qualifications (Nice To Have)

  • Previous experience in a digital environment.
  • Background in Process Integration or knowledge of yield topics (Yield/DFM) and Failure Analysis.
  • Experience with Automotive chips (ISO or Low Power design (UPF/CPF).

What Do We Offer?

  • Join a highly innovative microelectronics company working at the forefront of RISC-V and advanced SoC technologies.
  • Opportunity to play a key technical leadership role bridging industry and public research.
  • Collaboration with top-tier research institutions and industrial partners across Europe.
  • Flexible working conditions and hybrid work environment.
  • Competitive remuneration aligned with seniority and expertise.
  • Position based in Rome.

We are looking for outstanding people willing to join our mission to change this industry and help to build a better world
.

If you feel identified with Openchip, please contact us.

At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.

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