Sr. Dft Design Engineer, Aws Machine Learning Acceleration

Sr.DFT Design Engineer, AWS Machine Learning AccelerationAWS Utility Computing (UC) provides product innovations - from foundational services such as Amazon's Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS's services and features apart in the industry.As a member of the UC organization, you'll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation.Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago— even yesterday.Key Job ResponsibilitiesDevelop, implement and verify state-of-the-art Design for Test (DFT) architecturesWork with block designers to integrate DFT implementationsWork with physical design team to set up and implement DFT insertion flowDevelop high coverage and cost-effective DFT methodologiesPerform RTL coding and verificationParticipate in silicon debug and write scripts to effectively handle ATE related dataCommunicate and work with team members across multiple disciplinesAbout the TeamWe're a fast-paced, intellectually challenging team that provides leadership in applying new technologies to large-scale server deployments, continually improving performance, quality, and cost.We value high standards and encourage individuals ready to tackle industry-shifting challenges.Basic QualificationsBS degree in EE, CE, or CS5+ years of practical DFT experience with large processor and/or SoC designsKnowledge about industry-standard tools and practices in DFT, including ATPG, JTAG, MBIST, and trade-offs between test quality and test timeExperience with automation script developmentPreferred QualificationsMS degree in EE, CE or CSGood breadth of knowledge in chip design from micro-architecture through physical designGood knowledge of design verification (DV) simulation methodologiesExperience with large gate-level simulation setup and debug with SDFStrong programming and scripting skills in Perl, Python or TclExperience with industry-standard DFT/SCAN/ATPG toolsExperience with STA constraints development and analysis for DFT modesPractical experience with silicon debugAmazon is an equal-opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.Our inclusive culture empowers Amazonians to deliver the best results for our customers.If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, please visit for more information.Our compensation reflects the cost of labor across several US geographic markets.The base pay for this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic market.Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience.Amazon is a total compensation company.Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits.For more information, please visit .This position will remain posted until filled.Applicants should apply via our internal or external career site.#J-*****-Ljbffr