Staff Engineer Digital Design
4 giorni fa
Are you passionate about digital design and mixed-signal IP development?Do you want to be part of a team who generate synergies across Infineon applications through AMS Solutions?Are you eager to collaborate with a world-class team of engineers in a dynamic and innovative environment?Then our Design Enabling & Services team in Padova is waiting for youJob DescriptionAs a Digital Design Engineer, you will be specialized in the design and development of mixed-signal IPs for ASICs.Furthermore, you will also have the opportunity to work on cutting-edge projects, collaborating with a talented team of engineers to deliver high-quality IP solutions.In your new role you will:Design, develop, and verifydigital components ofmixed-signal IPs for ASICsWrite and maintain SystemVerilog codefor digital IP blocks, includingRTL design, simulation, and synthesisCollaborate with analog designersto ensure seamless integration of digital and analog componentsDevelop and executeverification plans, includingwritingtestbenches and assertionsPerformsimulation, synthesis, and place-and-route tasksusing industry-standard toolsDebug and optimize digital IP blocksto meet performance, power, and area requirementsWork closely with the verification teamto ensure IP quality and reliabilityParticipate indesign reviewsand contribute to theimprovement of design processes and methodologiesYour ProfileYou have excellent problem-solving skills, with the ability to debug complex digital designs.Your strong communication and collaboration skills allow you to work effectively in a team environment.You are also detailed oriented, able to manage multiple tasks, and adapt to evolving project requirements.You are best equipped for this task if you have:Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or similar field of studyAt least3 years of experience in digital design, with a focus on mixed-signal IPsProficiency in System Verilog, with experience in writingRTL code and testbenchesStrong understanding ofdigital design principles, including logic design, timing analysis, and clock domain crossingExperience withindustry-standard design tools, such assimulators, synthesizers, and place-and-route toolsFluency in English(mandatory)It is an advantage if you have:Experience with Spyglass, LEC, Synthesis, and ATPG toolsKnowledge of low-power design techniques and power management strategiesFamiliarity with scripting languages, such as Perl or PythonExperience with version control systems, such as Git, PerforceUnderstanding of analog-digital interface design principles and mixed-signal design flowsUnderstanding and design of digital filter principlesPlease send us your CV in English.Contact:Rita Costa,LinkedIn#WeAreIn for driving decarbonization and digitalization.As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT.Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals.Be a part of making life easier, safer and greener.Are you in?– At our R&D center in Padova we develop next generation Automotive applications –In Padova we combine Italian creativity with German operational excellence to develop innovative semiconductor solutions for clean, safe and smart cars.Here you will find a dynamic team made of highly skilled professionals from 15 different countries, who combine the experience of the senior engineers with the energy of young graduates.We are on a journey to create the best Infineon for everyone.This means we embrace diversity and inclusion and welcome everyone for who they are.At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities.We base our recruiting decisions on the applicant ´s experience and skills.We look forward to receiving your resume, even if you do not entirely meet all the requirements of the job posting.Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.Click herefor more information about Diversity & Inclusion at Infineon.#J-*****-Ljbffr
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Staff Digital Design Engineer — Mixed-Signal IP Leader
2 settimane fa
padova, Italia Infineon Technologies AG A tempo pienoA leading semiconductor company in Padova is seeking a Digital Design Engineer to design and develop mixed-signal IPs for ASICs. The role involves writing SystemVerilog code, collaborating with analog designers, and ensuring IP quality through rigorous verification. The ideal candidate should have a degree in Electrical Engineering and at least 3 years of...
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Staff Digital Design Engineer — Mixed-Signal Ip Leader
2 settimane fa
Padova, Italia Infineon Technologies Ag A tempo pienoA leading semiconductor company in Padova is seeking a Digital Design Engineer to design and develop mixed-signal IPs for ASICs.The role involves writing SystemVerilog code, collaborating with analog designers, and ensuring IP quality through rigorous verification.The ideal candidate should have a degree in Electrical Engineering and at least 3 years of...
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Padova, Italia Infineon Technologies Ag A tempo pienoAre you passionate about digital design and mixed-signal IP development?Do you want to be part of a team who generate synergies across Infineon applications through AMS Solutions?Are you eager to collaborate with a world-class team of engineers in a dynamic and innovative environment?Then our Design Enabling & Services team in Padova is waiting for you!Job...
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Padova, Italia Infineon Technologies AG A tempo pienoAre you passionate about digital design and mixed-signal IP development? Do you want to be part of a team who generate synergies across Infineon applications through AMS Solutions? Are you eager to collaborate with a world-class team of engineers in a dynamic and innovative environment? Then our Design Enabling & Services team in Padova is waiting for...
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