Principal Engineer

1 settimana fa

Lazio, Italia Analog Devices A tempo pieno

About Analog Devices, Inc. (ADI)'s Trinamic motor and motion control products transform digital information into precise physical motion, enabling Industry 4.0 performance in applications such as advanced robotics, automation, medical prosthetics, 3D printing, and more.The ADI Trinamic motor control ICs represent complete, efficient, small-footprint innovative solutions that can help reduce complexity and time to market for intelligent motion systems while supporting potential space and performance efficiency improvements.ResponsibilitiesLead Pre-Silicon verification for Motor Drivers and embedded Motion Control IC / SoC solutions.Defining verification strategy, test plans, tests and methodology for block / subsystem and chip-level verification based on product requirements and design specifications.UVM testbench architecture development and implementation of DV flow.Collaborate with cross-functional teams (IC Design, Firmware Development) to identify and resolve design and verification issues to achieve closure of code and functional coverage.Perform functional and performance verification of digital designs, including simulation, formal verification, and hardware emulation.Analyze metrics and verification KPIs to take proper actions to successfully achieve verification signoff.Mentor and guide junior verification engineers, providing technical leadership and support.Stay up to date with the latest verification technologies and best practices and drive their adoption within the team.Contribute to the continuous improvement of verification processes and methodologies.Desired Qualifications & ExperienceB.Tech / M.Tech with 8+ years of industry experience in Digital Pre-Silicon verification.Good understanding of SOC / Subsystem design concepts and design architectures.Hands on experience in developing, updating and debugging of Verilog, SV-UVM, SoC level testbenches is a must.Experience in closing the verification of block, subsystem level verification using industry standard metrics like code and functional coverage is a must.Setup and maintenance of verification environment and test benches.Formal verification: Define formal verification flow to check connectivity and functional verification.Perform gate level simulations with timing annotated.Strong knowledge of test-plan generation, coverage analysis, transaction level modelling, pseudo and constrained random techniques with SystemVerilog.In-depth knowledge of SystemVerilog-UVM and debugging of testbenches is a must.Assertion and formal knowledge are advantages.SystemVerilog, C / C++, SystemC, TCL / Python / shell-scripting.Experience in analog and mixed-signal verification or analog behaviour modelling (ADC / DAC / PLL / sensors) is an added advantage.Exceptional interpersonal and communication skills, collaborate and influence innovative design development / verification methodologies to a wider team spread across the globe.Quick to adopt new technologies with good problem-solving skills.Job Req Type: Experienced.Required Travel: Yes, 10% of the time.Shift Type: 1st Shift / Days.#J-*****-Ljbffr

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