Sr Staff R&D Engineer

2 settimane fa

Bardi, Italia Synopsys Inc A tempo pieno

In this role, you will be responsible for the Physical Implementation of high speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off, in close interaction and collaborative team work with multiple functional groups (front end, analog, CAD) and the product team.As well, you will be expected to lead a small team of engineers performing these same tasks.As a Sr Staff R&D Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56G/112G/224G PAM4/6 standards, all at the latest process nodes.The Mixed-Signal IP organization is seeking a highly motivated individual responsible for the physical implementation of complex Mixed signal IPs and test chips across multiple process technologies with a specific focus on very advanced high speed SERDES platforms.The successful candidate will have the following:12 + years of digital or physical design experience with recent contribution to project tape-outs, as a technical driver and/or project lead.Intimate knowledge of the full design cycle from RTL to GDSII, including chip level.Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniquesA solid engineering understanding of the underlying concepts of digital design and architecture, implementation flows and physical and timing signoffDevelopment of timing constraints and design architectures to ensure on-time delivery, and to meet or exceed power and area targetsExcellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers.Methodology driven with strong software and scripting skills (Perl, Tcl, Python); knowledge of CAD automation methods.Solid understanding of the challenges inherent in analog/digital interfaces.Autonomous, timely decision maker and able to cope with interrupts.Main Requirements:MSEE and 10+ years or BSEE and 12+ yearsPrevious project leadership experienceSolid understanding of digital / mixed signal verification flows and SOC integration challenges.Ability to travel internationally as required

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