Principal Analog Design Engineer

6 giorni fa


Pavia, Italia Lordan Associates A tempo pieno

OverviewPrincipal Analog Design Engineer – Pavia, Italy.Salary: €85,000 to €110,000 + Bonus + SIGNING BONUS + Paid Relocation.This role is a key position within our Optical PHY (CE-OPHY) team, which is part of our Central Engineering division.Our team is at the forefront of designing high-speed and optical transceivers for modern communication infrastructure.This technology is critical for addressing the explosive demand for bandwidth in mega data centers that power social media, video-on-demand, gaming, and other real-time data streams.We are dedicated to developing innovative, first-to-market chips and subsystem solutions that push the boundaries of data rates and power efficiency.ResponsibilitiesDesign & Architecture: Analyze and interpret block specifications, take ownership of transistor-level design, and select the most appropriate topologies.Design entire analog macros or IPs from initial concept to final mass production.Verification & Validation: Model and validate circuit blocks, supervise layout activities, provide clear guidelines, and conduct post-layout verifications to ensure design integrity.Collaboration & Leadership: Collaborate with other engineering teams to enhance existing solutions, participate in cross-functional meetings, train and mentor junior designers to build the team\'s expertise.Project Management: Manage pre-silicon tasks (simulation and modeling) and post-silicon tasks (lab characterization, debugging, correlating measurements to simulations) through to high-volume production.Candidate ProfileEducation & Experience: Master's degree or Ph.D. in Electrical Engineering or a related field is required, with ***** years of professional experience.Technical Skills: Proven experience in designing ICs from architecture definition through lab characterization and volume production.Strong background in analog design (multi-GHz range), supervising custom analog layout, using standard EDA CAD tools, and debugging to correlate simulations with measurements.Preferred Qualifications: Experience with multi-Gbps electrical SerDes or electro-optical transceivers.Knowledge of advanced CMOS nodes, including FinFET, is advantageous.Personal Skills: Strong communication, presentation, and documentation skills.Proficiency in Italian and English (minimum B2 level) is required.Work Model: On-site, full-time position located in Pavia, Italy.#J-*****-Ljbffr



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