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1 settimana fa
ResponsibilitiesDevelop verification plans in coordination with design leads and architects.Be responsible for planning building and maintaining verification test bench components and environments.Generate directed and constrained random tests.Run simulations and debug design and environment issues.Create functional coverage points, analyze coverage and improve test environment to target coverage holes.Craft automated verification flows for block and chip level verification.Apply knowledge of hardware description languages (VHDL/Verilog) and hardware verification languages (SystemVerilog/UVM) and logic simulators to verify complex designs.Work with other block and core level engineers to ensure a perfect verification flow.QualificationsMasters degree in Electrical Engineering Embedded Systems Computer Science or related fieldExcellent communication and interpersonal skills combined with the ability to collaborateFluency in EnglishDeep knowledge of SystemVerilog and UVMExperience developing scalable and portable test-benchesExperience with constrained random verification environmentsExperience defining coverage space writing coverage model analyzing resultsExperience with Assertion Based VerificationExperience in Formal Verification (Formal Linting Formal connectivity user property verification) is a plusExperience with Python Perl or TCLUnderstanding of AI and ML and their potential application to verificationApple is an equal opportunity employer that is committed to inclusion and diversityWe take affirmative action to ensure equal opportunity for all applicants without regard to race color religion sex sexual orientation gender identity national origin disability Veteran status or other legally protected characteristicsApple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilitiesEmployment Type: Full TimeExperience: YearsVacancy: 1#J-*****-Ljbffr
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