Junior Digital Verification Engineer
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Overview
In this role you verify advanced Digital and Mixed-Signal ASICs within an international semiconductor team. You design scalable verification environments and apply cutting-edge methods to ensure first-silicon success and product reliability. You collaborate across globally distributed teams to shape semiconductor solutions from concept to production. Your work drives verification excellence and efficiency through AI-assisted workflows and continuous process improvements. This is an opportunity to contribute to high-impact sensors and automotive ICs at Bosch Sensortec.
Retribuzione / Benefits
- bonus based on company performance
- additional benefits
Responsabilità
- Design and develop scalable, reusable verification environments for complex ICs to accelerate first silicon bring-up
- Apply functional and formal verification methodologies to validate digital designs and improve reliability
- Collaborate with engineers across multiple international locations in a globally distributed environment
- Contribute across the full product lifecycle from concept to production
- Document and improve verification processes, methodologies, and best practices to raise efficiency and knowledge sharing
Requisiti fondamentali
- Experience or strong interest in ASIC/SoC verification or a Ph.D. in Electrical Engineering, Computer Science, or related field with semiconductor focus
- Expertise in ASIC verification methodologies (UVM, formal verification, directed verification)
- Knowledge of digital circuit design (VHDL/Verilog, Digital IP) and verification of complex designs
- Hands-on experience with modern simulation, verification, and EDA tools
- Background in analog/mixed-signal modeling (wreal, MATLAB/Simulink, SystemC)
- Power-aware verification and UPF methodologies
- Scripting/automation skills (Python, Tcl)
- Interest in applying AI-assisted workflows to verification
- Proficiency in English (C1)
- Curiosity and creativity
- Proactive mindset and ownership
- Collaborative and cross-functional teamwork
- UVM
- Formal verification
- Directed verification
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