Senior/staff silicon physical design engineer

14 ore fa

Turbigo, Italia Axelera AI A tempo pieno

About UsAxelera AI is not a regular deep‐tech startup. We are building the next‐generation AI platform to support anyone who wants to help advance humanity and improve the world around us. In just four years we have raised $120 million, built a world‐class team of 220+ employees (including 49+ Ph Ds with more than 40 000 citations), and launched our MetisTM AI Platform, which achieves a 3–5x increase in efficiency and performance. Our global presence includes offices in Belgium, France, Switzerland, Italy, the UK, and the Netherlands.Position OverviewAs a Senior Silicon Physical Design Engineer at Axelera AI, you will play a crucial role in developing cutting‐edge multi‐core in‐memory compute So Cs. Leveraging your expertise in ASIC Physical Design from RTL to GDS, you will be responsible for all aspects of the design flow, including synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR sign‐off, and formal verification. You will collaborate closely with architecture and RTL teams to ensure successful project execution.Key ResponsibilitiesPerform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification.Generate constraints, perform timing analysis and optimization.Execute clock tree synthesis (CTS) and custom clock‐building techniques.Integrate IPs, including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs.Utilize EDA tools such as Primetime, Star RC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.Develop automation scripts in Python, Tcl, and Bash, and contribute to flow development.Debug and resolve technical challenges related to physical design.Collaborate with architecture, RTL, and verification teams.Qualifications10+ years of experience in Physical Design (RTL to GDS).Strong communication and teamwork skills.Expertise in all aspects of physical design.Hands‐on experience with leading EDA tools (Primetime, Star RC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre).Proficiency in clocking techniques and CTS.Experience in IP integration across various domains.Strong scripting skills (Python and Tcl).Proven problem‐solving and debugging capabilities.Fluent in English (spoken and written).Highly PreferredExperience in floorplanning and top‐level integration.Knowledge of chip‐package‐board co‐simulation and packaging.Experience working with EDA vendors to resolve tool issues.Understanding of semiconductor device physics and multi‐domain design.LocationWe offer a flexible working arrangement, with options to:Work from one of our Axelera AI offices (Leuven in Belgium; Amsterdam and Eindhoven in the Netherlands; Florence and Milan in Italy; or Bristol in the United Kingdom) if you are already based nearby.Work fully remotely from any European country (including the UK).Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven).

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