Senior Digital Design Engineer

1 giorno fa

Varese, Lombardia, Italia NXP Semiconductors Tempo pieno

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Overview In this role you will help design and implement advanced digital subsystems for automotive and industrial electrification. You will collaborate with architects, verification engineers, and cross-functional teams to define digital architecture and ensure robust RTL in SystemVerilog. You will address performance, power, area, safety, and testability trade-offs and drive design quality through verification and sign-off readiness. This position offers impact across mixed-signal projects, reuse of digital IP, and contribution to safety-compliant automotive developments. You will work in a global, collaborative environment focused on delivering high-quality mixed-signal solutions at scale. Retribuzione / Benefits
* equal pay commitment
* annual incentive opportunities
* equity
* competitive benefits package
* fair remuneration practices Responsabilità
* Develop RTL designs for complex digital blocks and subsystems using SystemVerilog/Verilog
* Contribute to digital architecture definition with senior designers and system architects
* Analyze design trade-offs for performance, power, area, safety, and testability
* Implement clocking, reset, and power management strategies
* Support IP integration and subsystem-level development
* Perform RTL verification activities including simulation, lint, CDC, and synthesis checks
* Collaborate with digital verification engineers for coverage and quality
* Support timing closure and implementation activities
* Participate in design reviews and sign-off readiness
* Support silicon bring-up, debugging, characterization, and root-cause analysis
* Work within mixed-signal project teams and promote reuse of digital IPs and methodologies
* Contribute to requirements definition and feasibility analysis
* Support multiple development phases from concept through production release
* Follow automotive standards for functional safety and quality
* Provide technical guidance to less experienced engineers
* Collaborate across international R&D sites Requisiti fondamentali
* Master's degree in Electrical Engineering, Electronics Engineering, or equivalent
* Minimum 7 years of experience in digital IC design
* Strong experience with RTL development using SystemVerilog/Verilog
* Experience with synthesis, timing constraints, and digital implementation flows
* Understanding of CDC, reset strategies, and low-power design concepts
* Familiarity with DFT fundamentals and design-for-test methodologies
* Experience in mixed-signal IC development environments
* Knowledge of digital verification methodologies and simulation-based verification
* Experience with industry-standard EDA tools (Synopsys, Cadence, Siemens EDA)
* Fluent written and spoken English
* Team collaboration
* Cross-functional communication
* Mentoring and knowledge sharing
* SystemVerilog/Verilog RTL development
* Synthesis and timing constraints
* Digital implementation flows

Senior Digital Design Engineer

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