Senior Digital Verification Engineer
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* company performance-related bonus
* additional benefits Responsabilità
* Design and develop scalable, reusable verification environments for complex ICs to accelerate silicon bring-up
* Apply functional and formal verification methodologies to validate digital designs and improve reliability
* Collaborate with engineers across international locations in a distributed development setup
* Participate across concept through qualification phases to shape semiconductor solutions
* Document and improve verification processes and best practices to boost efficiency and knowledge sharing Requisiti fondamentali
* 5+ years of professional ASIC/SoC verification experience
* Expertise in UVM, formal verification, and directed verification
* Development and debugging of verification environments for complex MS/SoC designs
* Hands-on with state-of-the-art simulation, verification, and EDA tools
* Analog and mixed-signal modeling (wreal, MATLAB/Simulink, SystemC)
* Power-aware verification and UPF, scripting in Python or Tcl
* Interest in AI-assisted engineering workflows to improve verification
* English proficiency (C1)
* Dipl./ MSc in electrical engineering or computer science or equivalent
* Passion for technology and quality
* Curiosity and creativity
* Proactive mindset and ownership
* ASIC/SoC verification
* UVM
* formal verification
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