Memory Design Engineer
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In this role you will support memory design and device enablement within Allegro’s Technology Development group. You’ll design and verify memory IP and NVM/DV structures, coordinate layout and floor planning, and help standardize memory components for a global design community. You’ll work across foundry processes and PDK environments to enable the product roadmap and enable cutting-edge semiconductor development. This role offers impact through direct contribution to BCD technology and cross‑functional collaboration.
Responsabilità- Design NVM and digital IP for silicon
- IP in silicon test and validation
- Coordinate design requirements, macro floor planning, and layout
- Characterize and standardize memory/digital IP for global use in a PDK
- Documentation of IP specifications and application use cases
- BSEE with +4 years of experience in memory and mix-signal transistor-level design, circuit verification, and silicon testing
- experience with memory and standard cells in liberty format and memory debug/diagnostics
- EDA skills: Cadence flows (Virtuoso, Genus, Innovus, Xcellium, Modus Test, Quantus/Calibre)
- HDL knowledge (Verilog, VerilogA, VerilogAMS); C and SystemVerilog a plus
- layout parasitics/leakage design trade-offs and sub-micron modeling challenges
- device physics understanding at transistor level (cross section, STI, DTI)
- ability to develop memory test/validation plans
- collaboration with cross-functional teams
- communication and documentation
- problem-solving mindset
- Memory design and IP development
- Memory testing and validation planning
- Digital components and interfaces (logic, EEPROM, JTAG, FPGA)