Senior Digital Verification engineer

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We are looking for a Digital Verification Engineer – SoC to join our MDRF-RFOC-DVCC Digital Verification team in Naples, dedicated to the digital verification of complex SoC/IP for automotive / industrial applications.

The selected candidate will work on SystemVerilog UVM testbenches, firmware / drivers in C, and Python scripts for automation, contributing to the entire verification cycle: from strategy definition to environment creation, up to coverage analysis and debug. Within the team we also use AI-assisted tools and methodologies to accelerate development, debug, and results analysis, and we expect the candidate to be curious and interested in leveraging these technologies in day-to-day activities.

• Define, in collaboration with architects and designers, the verification strategy at IP and/or SoC level.
• Develop and maintain UVM testbenches in SystemVerilog (environment, agent, sequencer, driver, monitor, scoreboard).
• Write and integrate C tests for subsystem and SoC verification in simulation and/or emulation environments.
• Develop Python scripts (and, when needed, bash/Tcl/Perl) for:
  • regression automation,
  • post-processing of results,
  • coverage analysis and report generation.
• Perform functional debug of failing test cases, interacting with the design (RTL) team and system architects.
• Run and debug gate-level simulations with SDF back-annotation, analyzing timing-related issues and collaborating with design and implementation teams to identify and resolve problems.
• Analyze and manage functional coverage and code coverage, proposing new tests or testbench improvements to meet quality targets.
• Use AI-assisted tools and workflows for:
  • generation and review of testbench code and scripts,
  • log analysis,
  • debug acceleration.
• Contribute to the continuous improvement of verification flows (methodologies, common libraries, guidelines, best practices).
• Produce clear and structured documentation for:
  • verification specifications,
  • testbench architecture,
  • test plans,
  • key results.

• Degree in Electronic Engineering, Computer Engineering/Science, Physics with an electronics focus, or related disciplines.
• Solid knowledge of digital verification of integrated circuits (RTL concepts, testbench, stimuli, checkers, coverage).
• Hands-on experience with SystemVerilog and UVM methodology:
  • development of UVM components (sequencer, driver, monitor, scoreboard),
  • environment configuration,
  • sequence and virtual sequence management.
• Good command of the C language for verification-oriented test/firmware driver development.
• Experience with Python for scripting and automation.
• Good knowledge and practical use of the Unix/Linux environment (shell, file system, batch jobs, compilation, basic scripting).
• Familiarity with major digital simulators (e.g. Cadence Xcelium, Synopsys VCS, Siemens Questa).
• Basic knowledge of version control flows (Git, SVN, DesignSync).
• Good command of written and spoken English.
• 5-8 years of experience in the role.

• Experience with SoC/IP verification (AMBA/AXI/APB/AHB buses, memory interfaces, peripherals, interrupt controllers, DMA, etc.).
• Basic knowledge of machine learning / AI and use of AI tools for:
  • code generation,
  • log analysis,
  • test and scenario creation.
• Knowledge of formal verification techniques (e.g. property checking, assertion-based verification) and familiarity with formal tools.
• Experience in ISO 26262 environments.
• Knowledge of other scripting languages (bash, Tcl, Perl) and related EDA tools (lint, CDC, STA) is a plus.