Digital Verification Engineer
2 settimane fa
Verification of integrated mixed signal and digital blocks and CMOS IC's
Creation of verification plans for mixed signal or digital devices
Development of verification environment and ensure proper verification coverage for enabling bug free silicon manufacturing
Creation of DV test cases and debugging of simulation results
You have a successfully completed university degree in Electronics or a related field
A minimum of 7 years of professional experience in digital design/verification with hands-on experience on relevant design/simulation tools is required
Knowledge of design verification methodologies, tools, and languages (Digital Mixed-Signal simulation, UVM, System Verilog, assertions etc.)
Experience in analog blocks modeling as well as knowledge in other areas of Digital Design such RTL design with HDL (Verilog/VHDL) for integrated devices, DFT and test-pattern generation is a plus
You have an analytical mind for solving complex problems and debugging design issues popping up in simulations
You are a team player, committed to deadlines and development discipline
Advanced communication skills and full proficiency in English is mandatory
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