Senior A&MS Layout Engineer
1 mese fa
Requirements
- In depth familiarity with layout of analog and mixed signal CMOS circuits
- Experience in development of SERDES subcircuit layout (ie. RX, TX, PLL, etc…)
- Experience in the following layout design techniques: Optimization for signal integrity (ie. clock/data routes, differential routing, shielding)
- Implementation of ESD design constraints, latch-up risk mitigation
- Familiarity with custom digital layout (logic cell layout and associated logic path routing)
- Layout design for reliability (ie. EM, IR, etc…)
- Design to optimize for parasitic layout effects (ie. matching, reliability, proximity effects)
- Familiarity in design for porting techniques
- Full custom analog layout design tool: Custom Compiler (or equivalent)
- Verification tools: ICV, Calibre, Star-RCXT, PERC
- Experience in working with Jira/Atlassian (or other such) tools
- Proven understanding of MS Office Suite of applications
- Exposure to scripting (ie. TCL, PERL, etc…)
Experience
- MSEE or BSEE with at least 5+ years of related experience.
- Resolves a wide range of issues in inventive ways.
- Exercises judgment and partners with others in selecting methods and techniques to obtain solutions.
- Contributes to complex aspects of a project.
- Receives little to no instructions on day-to-day work, occasionally receives general instructions on new assignments and projects.
- Establishes and develops approach to solutions.
- Work is autonomous and collaborative in nature.
- Provides regular updates to manager on project status.
- Represents the organization on business unit and/or company-wide projects.
- Guides more junior peers with aspects of their job.
- Networks with senior internal and external personnel in own area of expertise.
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