Design verification Engineer

3 settimane fa


Re, Italia Efficiencie tech solutions llp A tempo pieno
Job Description1. Graduate in Computer Electrical or Software Engineering from a leading engineering university2. Proven handson experience in logic design verification of 8 years3. Proven handson experience with SystemVerilog UVM of 4 years4. Experience working for projects in an international company of 2 years5. Proven handson experience in defining & developing SystemVerilog Coverage6. Experience in developing SystemVerilog Assertion (aka SVA)7. Solid scripting skills in one of the following scripting languages: Python Perl TCL or BASH8. Solid user experience in working on Linux based systems9. Solid user experience in working with one of Version Control Systems: CVS SVN GIT Perforce ClearCase Mercury10. Handson experience with imageprocessing designs in defence industry advantage11. Handson experience with FPGA design development advantage12. Experience with GIT version control system advantage13. Firmware programming experience in C advantage14. DevOps experience advantageKey Qualifications verification validation systemverilog sv uvm uvc sva python perl asic fpga logicdesign linux git svn devops.

systemverilog,design,devops,perl,linux,fpga,git



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