Application Engineer in DFT Design For Test

3 settimane fa

Milan, Italia Cadence Design Systems, Inc. A tempo pieno

Description

, Role and Key Responsibilities

This is an excellent opportunity to work on challenging and complex SoC projects with Cadence customers in the semiconductor domain.

The Application Engineer will:

Provide high level of technical customer support for our products related to digital Design For Test. Identify and track technical issues in Customers’ DFT design environment, prioritize these issues considering both Customer's & Cadence's needs and drive their resolution. Assist the Customer with DFT flow development, e.g. improve existing design methodologies, develop new methodologies that leverage Cadence tools & services Support technical evaluations (including Beta evaluations with Cadence R&D and the customer) of new digital EDA tools, flows and methodologies. Provide direct contribution to key design projects, e.g. be responsible for driving Cadence DFT for key tasks on these projects. Develop and maintain technical and soft skills to be seen as a trusted EDA tool specialist with a deep knowledge in Cadence's DFT tools. Work with the Cadence Sales team to identify additional sales opportunities.

Requirement, Experience, Education

The Application Engineer will:

Have good understanding of DFT concepts and methodologies (ATPG, SCAN, BIST, …) Have some knowledge on our SW tools: Modus, Genus, or similar tools from other EDA vendors. Have excellent communication and problem-solving skills Be prepared to visit Cadence customers in Southern Europe (France, Italy, Switzerland, …)

Experience in digital DFT design and possibly some of the following disciplines:

Synthesis STA RTL design and verification CAD support for Digital IC Design and related flows

And,

Good communication skills; Excellent team spirit

Fluent in English

2 to 4 years of experience in microelectronics/EDA industry

Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.

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