Senior Design Enablement Engineer
3 settimane fa
The Allegro team is passionate about providing intelligent solutions that move the world toward a safer and more sustainable future. With more than 30 years of experience developing advanced semiconductor technology, innovation with purpose touches every aspect of our business. From customer engagement and employee recognition to technology advancement and serving the local communities in which we maintain offices, innovation consistently drives our mission and definition of success.
As part of our innovation, we recognize that our team members are unique and that our work locations must be adaptable. At Allegro we flex.& is our approach to hybrid work that empowers managers and their team members to decide where and when work will be done. Ask what& can mean for you.
Allegro is looking for a Design Enablement Engineer to join Design Enablement team.. In this all-encompassing Design Enablement role, a qualified candidate will support and develop Foundry technology streams, process design kit (PDK) components, EDA tools, and mixed-signal design methodologies. The person will Act as first interface for issues resolution in regard to PDKs, Design tools/licensing and the Design Environment and capability to escalate issues to proper PDK/EDA/ methodologies development teams.
Responsibility:
Design and support internal/external PDK, IP Management, and QMS (Quality Management System) for Allegro BU design centers.
Design and support PDK design methodologies.
Develop design/application documentation for a mixed-signal design community.
Design and support BCD/BI-CMOS PDK and Technology streams.
Work with design centers to ensure standardization and centralization of the design environment, creating re-use capability, and developing information sharing mechanisms and participating in cross-functional team collaboration.
Develop custom tool/methodologies based on BU (Business Unit) requirements.
Qualifications:
A qualified candidate requires a BSEE or MSEE degree in a related field or equivalent, related experience and minimum of 2 years of related work experience including a good understanding of PDK and technology streams using EDA tools. Excellent communication skills (written and verbal) are required.
Must also have the following:
A working understanding of the design to tape-out workflow (schematic, simulation, layout, physical verification, MASK/GDS)
Knowledge of BCD/BI-CMOS fabrication methods.
Working understanding of PDK/Technology development components to include design rules, mask-gen, models, process parameters, test-chips, and design integration.
Familiarity with web based design management tools, documentation, and bug tracking systems
Ability to participate in an aggressive learning and problem-solving team environment.
Basic understanding of modeling concepts & simulation of digital circuits, and systems engineering.
Top-Down Mixed Signal Design Methodologies to include PDK/Simulators.
Good understanding of device physics at the transistor design level (cross section, STI, DTI, field plating)
Fundamental understanding of Analog and Mixed-Signal Circuit Design
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