Analog Design Engineer

1 mese fa

Lazio, Italia Confidenziale A tempo pieno

Studying the specification of the device under test Defining the IP test specification in closed collaboration with design leaders, verification architect and product definers Developing the UVM simulation environment drivers, monitors, checkers and assertions and bridge it with mixed signal verification Developing and running digital and top-level simulations according to the verification plan Ensuring 100% coverage prior tapeout Preparing and holding design verification reviews Creating and maintaining regression test suites Reporting bugs, proposing solutions and followingtheir resolution You will work closely with digital designers and verification engineers as well as test and validation engineers to support both pre-silicon verification and post-silicon validation. This is an opportunity for a skilled verification engineer to grow quickly into leadership. Working in a strong technical biased environment, you will develop your competencies and will have the opportunity of evolving in both technical or project responsibilities. If you have the passion for innovation, the desire to challenge yourself and want to put your creativity in enabling the new mobility experience with electric autonomous cars, this is the right opportunity to join the leader in automotive semiconductor. Your Profile:
BS|MS in EE and 5 years of hands-on experience on digital verification methodologies MDV, formal Strong experience writing IP verification plans, creating test benches and automating regression test suites, preparing and presenting detailed verification reviews Understand and debug digital RTL Working knowledge of state of the art EDA tools:
Cadence Incisive, Cadence Vmanager Background in design and verification languages and methodologies Verilog, SystemVerilog, UVM, SVA. Experience in configuration database management DesignSync, Git, SVN Scripting skills Python preferred or Perl or TCL. Good communication skills both French and English Optional Experience in formal verification SVA, PSL, Jasper Experience with mixed signal analog, digital verification methodologies Experience developing behavioral models for analog IPs both event-driven|WREAL and conservative|Verilog AMS Understand and debug analog schematics Tools:
Cadence Virtuoso, Collabnet, Jenkins Summary Location:
Milan; Gratkorn Type:
Full time

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