Senior Digital Design Engineer for High-Speed SerDes Products
1 mese fa
Job Overview
We are seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow to join our team of experts in mixed-signal design and verification.
The candidate would work on designing and verifying high-end mixed-signal designs, from specification development to performing functional and performance tests on prototype test-chips.
This is an excellent opportunity to work with an expert team responsible for delivering high-end mixed-signal designs and to contribute to the development of our dynamic PHY IP.
About Synopsys
Synopsys is at the heart of innovations that change the way we work and play. We power the Era of Smart Everything with the world's most advanced technologies for chip design and software security.
Job Description
As a Senior Digital Design Engineer, you will be responsible for:
- Designing and verifying high-speed serializer and data recovery circuits
- Developing and maintaining existing SERDES PHY IPs supporting multiple protocols
- Collaborating with Application Engineers for customer support and resolving technical issues with Analog and PR teams
Required Skills and Qualifications
To be successful in this role, you should have:
- BSEE or MSEE plus a minimum of 4 years of digital design and verification experience in the industry
- Good experience in writing block-level test-cases including constrained directed random tests
- Must be familiar with Verilog and VCS
- Good knowledge of back-end synthesis tools DC/PT is required
- Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows
Benefits
At Synopsys, we offer:
- A competitive salary: $120,000 - $180,000 per year
- A comprehensive benefits package
- Opportunities for professional growth and development
- A dynamic and inclusive work environment
Preferred Experience
RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog are preferred skills. Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures are also valuable experiences.
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