Senior Engineer for Digital Validation

5 giorni fa


Bardi, Emilia-Romagna, Italia Synopsys A tempo pieno
About the Role:
As a Senior Engineer for Digital Validation, you will work with a skilled team of digital and mixed-signal engineers to deliver high-end mixed-signal designs from specification development to functional and performance testing on prototype test-chips.

Main Responsibilities:
• Develop and implement testbenches for high-speed digital designs
• Conduct functional coverage, assertion coverage, and code coverage analysis
• Collaborate with the team to create and track test plans, evaluate failure cases, and run gate-level simulations

Key Qualifications:
• Bachelor's or Master's degree in Electrical Engineering with 15+ years of digital validation experience in the industry
• Proficient in Verilog and System Verilog, with hands-on experience in writing complex testcases
• Familiarity with code quality metrics and UVM methodology

Estimated Salary: $110,000 - $160,000 per year.

About Synopsys:
Synopsys offers the world's most advanced technologies for chip design and software security. Our Silicon IP business integrates more capabilities into an SoC—faster, meeting unique performance, power, and size requirements of target applications.

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