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Senior Design Engineer

2 mesi fa

Milano, Lombardia, Italia Ferroelectric Memory A tempo pieno
About the Role

We are seeking a highly skilled DDR RTL Design Engineer to join our team at Ferroelectric Memory. As a key member of our design team, you will be responsible for the development of high-speed DDR control logic interface, including command decode, address registers, mode registers, data path, and clock tree.

Responsibilities
  • Design and verification of high-speed DDR control logic interface
  • Perform synthesis, timing, and power analysis
  • Optimize performance, power, and area parameters
  • Collaborate with AMS, verification, and layout teams to ensure compliance with JEDEC specifications
Requirements
  • 8+ years of experience in high-speed interface design
  • DDR4 RTL design experience for memory or controller devices
  • Familiarity with industry-standard design and simulation tools (e.g., VDI, Xcelium, Genus, Conformal)
About Us

Ferroelectric Memory is a dynamic company that has emerged as a significant player in the Memory industry. We are committed to innovation and excellence, and we offer a competitive salary, inspiring work environment, flat hierarchies, and opportunities for personal and professional growth.