ASIC Digital Verification Engineer

2 giorni fa


Bardi, Emilia-Romagna, Italia Synopsys A tempo pieno

Job Description

At Synopsys, we're looking for a skilled Digital Verification Engineer to join our team. As a key member of our mixed-signal design and verification team, you'll be responsible for verifying current and next-generation PAM-based SerDes products. Your exceptional knowledge in digital verification, especially in high-speed digital designs, will be invaluable in this role.

Main Responsibilities:

• Develop and implement modular constrained-random testbenches in Verilog and System Verilog
• Perform functional coverage, assertion coverage, and code coverage to ensure high-quality designs
• Create and track test plans, identifying and evaluating failure cases
• Collaborate with a skilled team of digital and mixed-signal engineers to deliver high-end mixed-signal designs

Key Qualifications:

• BSEE or MSEE with 10+ years of digital verification experience in the industry
• Expertise in writing complex testcases in Verilog and System Verilog
• Familiarity with code quality metrics and UVM methodology
• Excellent organization and communication skills

At Synopsys, we're at the heart of the innovations that change the way we work and play. Our Silicon IP business offers the world's broadest portfolio of silicon IP, integrating more capabilities into an SoC—faster. If you share our passion for innovation, we want to meet you.



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