Senior DFT Engineer, SSG

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re‑imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.Work hard. Have fun. Make history.We are seeking a seasoned and strategic Sr DFT Engineer to lead end-to-end Design‑for‑Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands‑on ownership, and proven leadership in taking chips from design to volume production.As a Senior DFT Engineer, you will be both the technical owner and hands‑on driver of the DFT strategy and execution across complex, high‑performance SoCs. This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug. You will work alongside world‑class design, validation, and test teams to ensure first‑pass silicon success and scalable production test readiness. Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability — from early DFT architecture planning to high‑volume silicon bring‑up and yield ramp.Key Job ResponsibilitiesLead development & implementation of DFT architecture including system level DFT for a full chipWrite and guide others in writing design flow and project documentationOwn DFT planning, milestone tracking, and cross‑functional checklist reviewsOversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlistsReview and sign‑off SoC level DFT mode timing closure using static timing analysisDrive the sign‑off on a generation of high‑quality test and debug patterns for high coverage on siliconKeep informed on and introduce new technology into Design‑for‑Test process as appropriateBasic QualificationsBachelor's degree in Electrical Engineering or a related field15+ years in SoC/ASIC DFT, including 3+ years leading DFTProven DFT experience leading multiple SoCs/ASICs (end‑to‑end) from architecture to high‑volume productionDFT Architecture expertise: Scan architecture, compression, and ATPG implementation for high fault coverage and test qualityMBIST, BISR, and BIHR flows, including advanced shared‑bus memory BIST integrationIEEE 1149.x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architecturesDFT‑aware STA closure, including constraint generation and timing convergence strategies for shift and capture pathsRTL and gate‑level debug, including mismatch triage and simulation correlation. Insertion and validation of EFUSE & OTP controllers and related structures during DFT implementationTool proficiency: Deep hands‑on experience with Tessent / industry standard EDA tools, including IJTAG ICL extraction and PDL modelingDFT logic insertion, pattern generation, and diagnosticsExperience in writing verilog/system verilog RTL related to DFT logic designLead DFT‑to‑ATE handoff, including driving generation and sign‑off of high‑quality test and debug patterns to meet DFT coverage targetsPattern validation, format conversion, and debugging across wafer sort and final test. Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvementsDrive post‑silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysisAbility to build and maintain scalable DFT automation flows using Python, Tcl, or PerlProven success driving cross‑functional teams involving RTL, physical design, validation, PE, and manufacturingKnown for being proactive, detail‑oriented, and independently accountable for tapeout and post‑silicon successPreferred QualificationsMaster's degree or Ph.D. in Electrical Engineering or related fieldLeadership: Led multi‑site/global DFT teams, mentoring engineers and managing design reviewsDriven design‑for‑test planning in collaboration with customers or design services partnersStrong understanding of DFT‑aware yield improvement and failure analysis, including DPPM reduction strategiesAbility to correlate pre‑silicon vs ATE pattern behavior and debug marginality/escape issuesExposure to Design‑for‑Debug features like trace buffers, signature capture, and observability enhancementOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.#J-18808-Ljbffr