MEMS Analog Mixed Signal Verification

OUR STORY
At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.

When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.

Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.

Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.

YOUR ROLE
The position is aimed at Analog Models Implementation Engineer with previous experience in mixed signal and digital simulations of ASICs.
The preferred seniority is 1 to 2 years of experience.
The candidate will be part of Mixed verification team of MEMS sGROUP and he/she/div will have the opportunity to follow all the ASIC verification process from specification definition up to final product industrialization

The candidate responsibilities includes definition and model development, as well as definition and development of verification test bench, verification components, test case development for simulation, debugging failures and creating simulation cases for various studies. As an experienced professional, work with the cutting-edge verification methodologies on Subsystem level and SoC level.

Your Skill & Experiences
The required background of study is Electronic Engineering.

The ideal candidate has a good knowledge of reading custom circuit schematics and understanding functionality (e.g., ADC, DAC, comparators, ...), SystemVerilog RNM and Verilog-AMS modeling languages, Analog models definition and implementation, Analog models verification (vs. schematics) and validation (vs. spec), Analog and digital simulations, SystemVerilog Analog Assertions, Bug analysis and reporting, Scripting languages like Python.

Basic knowledge of SystemVerilog and UVM methodology, Coverage and tools for file versioning control system.

A plus will be considered the knowledge of tools and environments for mixed-signal simulations Cadence based (Virtuoso, Spectre, Xcelium)

The candidate has also soft skills such as good
communication
, fluent in English,
team working
and
collaboration
across all the entire MEMS sGROUP Design team.

This position involves a hybrid working mode.
ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.

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