SR ENGINEER, DESIGN Avezzano, L'Aquila, Italy Posted 20 hours ago

## SR ENGINEER, DESIGNAvezzano, L'Aquila, ItalyApply NowFind out how well you match with this jobJob ID: JR114714Our vision is to transform how the world uses information to enrich life for *all*.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design/Senior Design Engineer – Auto Place & Route / Digital Implementation (NVE Engineering)Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department IntroductionThe Non-Volatile NAND Design Engineering group is responsible for the design and optimization of analog, digital, and mixed-signal circuits enabling advanced NAND Flash memory products. Close collaboration with cross-functional teams ensures scalable, manufacturable, and reliable solutions across technology nodes. Position OverviewAs a Digital Implementation / Auto Place & Route Engineer in the NVEG organization at Micron Semiconductor Italia, you will drive the physical implementation of advanced NAND Flash digital designs from synthesized netlist through tape-out.
In this role, you will own block
- and subsystem-level implementation, including floorplanning, power planning, placement, clock tree synthesis, routing, optimization, and physical sign-off. You will partner with RTL, verification, DFT, analog, custom layout, CAD, and product teams to achieve performance, power, area, reliability, and schedule targets. ResponsibilitiesResponsibilities include, but are not limited to:
• Own end-to-end RTL-to-GDSII physical implementation for complex digital blocks and subsystems using automated place-and-route flows.
• Develop and optimize floorplans, power distribution networks, placement, clock tree synthesis, routing, and post-route optimization strategies.
• Drive timing closure across multi-mode, multi-corner scenarios through constraint development, static timing analysis, ECO implementation, and working directly with logic designers.
• Perform and resolve physical sign-off checks, including DRC, LVS, antenna, signal integrity, congestion, IR-drop, electromigration, and power analysis.
• Collaborate with RTL, DFT, analog, custom layout, CAD, package, and verification teams to ensure robust integration and tape-out readiness.
• Develop scripts, metrics, and reusable methodologies to automate implementation flows, improve quality of results, and reduce turnaround time. AI Enablement and ProductivityThe candidate is expected to leverage AI-powered tools and data-driven methodologies to improve engineering productivity, accelerate problem solving, support design analysis, and enhance technical decision making. Responsibilities may include:
• Using AI-assisted engineering tools for script generation, review, debug, and documentation.
• Applying AI-enabled analysis to timing, congestion, power, routing, and physical verification datasets.
• Finding opportunities to automate repetitive implementation, reporting, and debug activities.
• Evaluating emerging AI capabilities to improve flow efficiency, predictability, and quality of results.
• Collaborating with multi-functional teams to integrate AI automated workflows into digital implementation activities. Minimum Qualifications
• M.
S. or Ph.
D. in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• Hands-on experience with digital physical design and automated place-and-route flows for complex ASIC, SoC, or memory designs.
• Proficiency with industry-standard implementation and sign-off tools (e.g., Cadence Innovus/Tempus or Synopsys Fusion Compiler/IC Compiler II/PrimeTime).
• Strong understanding of floorplanning, clock distribution, timing closure, low-power design, signal integrity, and physical verification.
• Experience with scripting and flow automation using Tcl, Python, Perl, or equivalent languages.
• Strong problem-solving, documentation, and communication skills, with the ability to work effectively in global multi-functional teams. Preferred Qualifications
• Experience with NAND Flash, other non-volatile memories, or large mixed-signal SoCs, including integration of digital blocks with custom and analog macros.
• Experience with advanced technology nodes, hierarchical implementation, low-power techniques, ECO flows, and tape-out/sign-off closure. The base salary range that Micron estimates it could pay in for this position full-time is:43.000,00 €
- 74.000,00 € per year, with B3 CCNL Level. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position. Within the range, individua