Senior RTL

3 ore fa

Montebello della Battaglia, Lombardia, Italia ams Italy S.r.l. Tempo pieno

ams Italy S.r.l.

Aumenti le sue possibilità di ottenere un colloquio leggendo la seguente panoramica di questo ruolo prima di candidarsi.

seeks a Technical Leader for architecture and RTL development of high-speed digital subsystems in communication ICs and mixed-signal SoCs.

You will define architectures, lead RTL development, and drive design reviews while mentoring engineers.

Requirements include MSc/PhD in Electrical Engineering and 10+ years in digital IC design with RTL (Verilog/SystemVerilog). xysqume

Knowledge of high-speed interfaces like UCIe/PCIe is a plus.