Senior RTL
2 giorni fa
Montebello della Battaglia PV, Provincia di Pavia; Lombardia, Italia
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Tempo pieno
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ams Italy S.r.l. seeks a Technical Leader for architecture and RTL development of high-speed digital subsystems in communication ICs and mixed-signal SoCs. You will define architectures, lead RTL development, and drive design reviews while mentoring engineers.
Requirements include MSc/PhD in Electrical Engineering and 10+ years in digital IC design with RTL (Verilog/SystemVerilog). Knowledge of high-speed interfaces like UCIe/PCIe is a plus.