Verification Application Specialist
4 settimane fa
Cadence Design Systems, Inc. is seeking a skilled Verification Application Specialist to join our team. This role will involve working closely with customers to resolve technical issues, support technology adoption, and identify opportunities and risks associated with those activities.
Key Responsibilities:
- Provide direct technical pre-sales support for Cadence Verification products, leveraging a solid understanding of the complete verification flow.
- Manage strategic customer evaluations/benchmarks of Cadence verification solutions to establish technology differentiation and assert Cadence competitive advantages.
- Assist customers in adopting Cadence technology by providing Verification methodology and tool knowledge to design and verification engineers, validated through successful implementation.
- Drive best practices and lessons learned from delivering training, benchmarks, and customer interactions back into product development and Cadence field engineers.
- Perform methodology assessments, improve existing design/verification methodologies, and develop new ones that leverage Cadence technology and services.
Requirements:
- Masters degree in Electronic/Micro-Electronic Engineering or equivalent.
- 3-4 years of experience in hands-on Verification.
- Experience with Hardware Design and Verification languages, including Verilog, VHDL, System Verilog, and UVM.
- Good understanding of common verification flows and methodologies, such as UVM, Coverage-Driven Verification, Assertion-based Verification, Low-Power Verification, and Software Driven Verification.
- Experience with Unix/Linux environment, including scripting languages.
Preferred Qualifications:
- Experience in Formal property checking (PSL or SVA).
- Knowledge of one or more of the following languages in the context of Design & Verification: UPF, C/C++/System-C/TLM/Specman.
- Familiarity with the full SoC design flow.
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