Senior Verification Engineer
4 settimane fa
At Cadence, we are seeking a skilled Application Engineer System Verification to join our team in Milan, Italy. This role plays a crucial part in resolving customer issues, supporting technology adoption, and identifying opportunities and risks associated with those activities.
Key Responsibilities:
- Provide direct technical pre-sales support for Cadence Verification products, leveraging a solid understanding of the complete verification flow.
- Manage strategic customer evaluations and benchmarks of Cadence verification solutions to establish technology differentiation and assert competitive advantages.
- Assist customers in adopting Cadence technology by providing verification methodology and tool knowledge to design and verification engineers.
- Drive best practices and lessons learned from delivering training, benchmarks, and customer interactions back into product development and field engineering.
Requirements:
- Master's degree in Electronic or Micro-Electronic Engineering or equivalent.
- Around 3-4 years of experience in hands-on Verification.
- Experience with Hardware Design and Verification languages, including Verilog, VHDL, System Verilog, and UVM.
We're looking for a talented individual with a strong understanding of common verification flows, methodologies, and protocols. If you're passionate about verification and have experience with Unix/Linux environments, this could be the perfect opportunity for you.
In this role, you will have the chance to work closely with our Sales team, support technical sales campaigns, and develop strong communication skills. Additionally, you will have the opportunity to travel to customer sites and interact with customers.
Fluency in English and Italian is essential, and experience with formal property checking and languages like UPF, C/C++, or System-C is a plus.
Join us in making an impact in the world of technology and help us solve complex verification challenges.
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