Application Engineer System Verification Specialist

4 settimane fa

Milano, Lombardia, Italia Https:Www.Energyjobline.ComSitemap A tempo pieno

Job Purpose:

The successful candidate will be responsible for working independently and collaboratively with other team members to resolve customer issues, support technology adoption, and identify opportunities and risks associated with those activities.

Liaising with the RD and Marketing organizations to communicate customer requirements, influence product direction, and validate solutions will be a key aspect of this role.

The Application Engineer will work closely with the Sales team to support technical sales campaigns and develop the skills needed to demonstrate and adapt solutions to meet customer requirements.

Additionally, the AE will develop the ability to deliver training courses and workshops covering the Functional Verification Platforms and mature into a strong team member, leading projects and initiatives.

The position will involve travel to customer sites and significant interaction with customers.

Responsibilities:

Provide direct technical pre-sales support for Cadence Verification products, leveraging a solid technical understanding of the complete verification flow.

Manage strategic customer evaluations/benchmarks of Cadence verification solutions to establish technology differentiation and assert Cadence competitive advantages.

Assist customers in adopting Cadence technology by providing Verification methodology and tool knowledge to design and verification engineers, validated through successful implementation.

Drive best practices and lessons learned from delivering training, benchmarks, and customer interactions back into product development and Cadence field engineers; build understanding of the customer's needs and of the competition's technology and sales strategies.

Perform methodology assessments, improve existing design/verification methodologies, and develop new ones that leverage Cadence technology and services.

Take part in technical campaigns to enable our customers to adopt existing and new technologies and solutions.

Requirements:

The candidate should have a Master's degree in Electronic/Micro-Electronic Engineering or equivalent.

Around 3 to 4 years of experience in hands-on Verification is required.

Experience of Hardware Design and Verification languages, including Verilog, VHDL, System Verilog, and UVM, is necessary.

A good understanding of common verification flows and methodologies, such as UVM, Coverage-Driven Verification, Assertion-based Verification, Low-Power Verification, and Software Driven Verification, is essential.

Experience and knowledge of protocols like AMBA, Ethernet, USB, PCIe, and MIPI are also required.

Experience with Unix/Linux environment, including scripting languages, is necessary.

Of advantage would be:

Experience in Formal property checking (PSL or SVA) and knowledge in one or more of the following languages in the context of Design Verification: UPF, C/C++/System-C/TLM/Specman.

Familiarity with the full SoC design flow is also beneficial.

Excellent problem-solving skills and good communication skills are a must.

Team orientation, mature work attitude, and good judgment under pressure are necessary.

Ability to travel in Southern Europe and worldwide is required.

Fluent in English and Italian, speaking and writing is essential; French language knowledge is of advantage.

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