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milano, Italia NXP Semiconductors A tempo pienoEvaluation and Design of GaN‑Based Gate Driver Architectures for High‑Efficiency Inverter ModulesJoin to apply for the Evaluation and Design of GaN‑Based Gate Driver Architectures for High‑Efficiency Inverter Modules role at NXP Semiconductors.Overall purpose: to investigate the feasibility and advantages of Gallium Nitride (GaN) technology for...
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Milano, Italia Nxp Semiconductors A tempo pienoA leading semiconductor company in Milan is seeking an intern to work on the evaluation and design of GaN-based gate driver architectures for high-efficiency inverter modules.This internship involves conducting technology analysis, gate driver architecture design, and performance validation.Ideal candidates should have a solid background in analog circuit...
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Evaluation and Design of GaN-Based Gate Driver Architectures for High-Efficiency Inverter Modules
4 ore fa
Evaluation and Design of GaN‑Based Gate Driver Architectures for High‑Efficiency Inverter Modules Join to apply for the Evaluation and Design of GaN‑Based Gate Driver Architectures for High‑Efficiency Inverter Modules role at NXP Semiconductors . Overall purpose: to investigate the feasibility and advantages of Gallium Nitride (GaN) technology for inverter modules compared to SiC MOSFETs and IGBTs. The project is divided into three phases. Phase 1: Technology Analysis and Benchmarking Objective: conduct an in‑depth study of GaN for inverter applications. Activities: Review state‑of‑the‑art literature and technical papers to understand current trends and advancements in GaN‑based power electronics. Benchmark GaN against SiC and IGBT in terms of switching speed, efficiency, thermal performance, reliability, and cost. Analyze adoption by major OEMs and semiconductor companies. Collaborate with NXP’s Application and Product Definition Team for insights on GaN adoption strategies. Expected Outcome: a comprehensive report summarizing GaN advantages, limitations, and market positioning for inverter modules. Phase 2: Gate Driver Architecture Design for GaN Objective: develop and validate a gate driver architecture optimized for GaN devices. Activities: Address GaN requirements: high‑speed switching, low parasitic inductance, robust protection. Perform analog design: architecture definition, behavioral modeling, simulation, PVT analysis. Ensure manufacturability and reliability standards are met. Support layout design: consider parasitic effects, signal integrity, and layout performance. Expected Outcome: a fully simulated and optimized gate driver ready for prototyping. Phase 3: Bench Characterization and Validation Objective: validate the performance of a previous‑generation GaN gate driver in NXP’s laboratory. Activities: Conduct bench testing and waveform analysis. Identify critical issues and limitations. Document findings in a detailed characterization report, including measured performance versus simulation and recommendations for improvement. Expected Outcome: a validation report highlighting gaps and providing actionable insights for next‑generation designs. Key Deliverables Literature review and benchmarking report on GaN vs. SiC/IGBT technologies. Gate driver architecture design documentation, including simulations and layout considerations. Bench characterization report of the previous‑generation gate driver. Required Skills Analog circuit design and simulation (SPICE‑based tools). Layout design (Cadence Virtuoso or equivalent). Power electronics fundamentals. Laboratory measurement techniques (oscilloscopes, power analyzers). Collaboration with cross‑functional teams (Application Engineering, Product Definition). Seniority level: Internship. Employment type: Internship. Job function: Other. Industries: Semiconductor Manufacturing, Computers and Electronics Manufacturing, Software Development. Location: Milan, Lombardy, Italy. Referrals increase your chances of interviewing at NXP Semiconductors by 2×. #J-18808-Ljbffr
