ASIC Digital Design, Sr Engineer
2 mesi fa
Seeking a highly motivated and innovative design engineer with background in high-speed protocols. Working as part of an experienced digital design and verification team. The position offers an excellent opportunity to work with experts on several fields. The candidate will be involved at specify, design and implement phases of state-of-the-art products.
Key responsibilities:
- Study standard specifications published by JEDEC
- Define micro architecture at block level based on IP architecture
- Work on RTL design based on predefined coding style, SVA is included
- Clean RTL check violations in lint, CDC, DFT and synthesis
- Run block level test to speed up IP verification
- Work with verification to debug and fix RTL issues
- Check synthesis timing and improve RTL design if required
Required Skills:
- 1-year of relevant IP design experience
- Desire to learn and explore new technologies
- Demonstrate good investigation and problem-solving skills
- Be familiar with IP design flow and good at RTL design
- Solid RTL debug capability
- Knowledge in HBM/DDR and interface technologies such as UCie, PCIe, USB is a plus
- Knowledge in FrontEnd and/or BackEnd synthesis is a plus
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ASIC Digital Design, Sr Engineer
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Pavia, Italia Synopsys A tempo pienoSeeking a highly motivated and innovative design engineer with background in high-speed protocols. Working as part of an experienced digital design and verification team. The position offers an excellent opportunity to work with experts on several fields. The candidate will be involved at specify, design and implement phases of state-of-the-art products.Key...
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ASIC Digital Design, Sr Engineer
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Pavia (PV), Italia Synopsys A tempo pienoSeeking a highly motivated and innovative design engineer with background in high-speed protocols. Working as part of an experienced digital design and verification team. The position offers an excellent opportunity to work with experts on several fields. The candidate will be involved at specify, design and implement phases of state-of-the-art products....
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ASIC Digital Design, Staff Engineer
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Pavia, Italia Synopsys A tempo pienoWe are seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation PAM-based SerDes products. Strong theoretical and practical background in high-speed serializer...
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Pavia, Italia Synopsys A tempo pienoWe are seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation PAM-based SerDes products. Strong theoretical and practical background in high-speed serializer...
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Pavia (PV), Italia Synopsys A tempo pienoAs an ASIC Physical Implementation, Sr Staff Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56/112/224G standards. The digital implementation organization is seeking a motivated person responsible for the physical implementation of complex IPs and testchips across multiple process technologies...
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