Senior Digital Design Engineer

1 mese fa

Milan, Italia Allegro MicroSystems A tempo pieno

The Allegro team is passionate about providing intelligent solutions that move the world toward a safer and more sustainable future. With more than 30 years of experience developing advanced semiconductor technology, innovation with purpose touches every aspect of our business. From customer engagement and employee recognition to technology advancement and serving the local communities in which we maintain offices, innovation consistently drives our mission and definition of success.

As part of our innovation, we recognize that our team members are unique and that our work locations must be adaptable. At Allegro we flex.& is our approach to hybrid work that empowers managers and their team members to decide where and when work will be done. Ask what& can mean for you.

SUMMARY:

In this position, you will be part of a growing and dynamic team that primarily focuses on developing power management and lighting applications IC products.

You will have the opportunity to work with industry leading customers to develop advanced solutions for Automotive, Industrial, Communications and Computer systems.

RESPONSIBILITIES:

Interpreting requirements specification

Taking part in the specification phase of IC

Block and top-level digital design from specification to synthesized and STA clean netlist

Interface with physical implementation team for the definition of physical, timing and DFT constraints

Interface with product development team to develop test strategy.

QUALIFICATIONS:
Prospective candidates should have a PhD or master's degree (or equivalent) in Electronics or a related field and a solid experience in mixed signal IC design. The candidate should be proficient in developing block and top-level timing constraints for STA and P&R handoff.

Competent in digital design and DFT techniques

Knowledge of front-end RTL design using Verilog or VHDL

Experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog/System Verilog

Good verbal and written communication skills

Ability to work in a multi-cultural team environment.

Good presentation skills in English and the ability to present information in a clear and concise manner.

A high level of commitment and self-motivation

The ability to work as part of a world-wide development team with diverse engineering disciplines.

DESIRED QUALIFICATIONS:

Familiarity with serial interfaces such as SPI, I2C, UART, Manchester, CAN, etc.

Familiarity with Cadence toolsets, Matlab, Simulink modeling.

Experience in developing verification environments in SV/UVM and using SVA.

Knowledge of Tcl and Python or similar.

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