Digital Verification Engineer

2 settimane fa


Pavia, Lombardia, Italia Synopsys A tempo pieno
Senior Digital Verification Engineer

We are seeking a highly skilled and innovative digital verification engineer to join our team at Synopsys. As a key member of our mixed-signal design and verification team, you will be responsible for verifying current and next-generation PAM-based SerDes products.

Main Responsibilities:
  1. Design and develop modular constrained-random testbenches in Verilog and System Verilog
  2. Perform functional coverage analysis and assertion coverage
  3. Develop and track test plans to ensure comprehensive verification
  4. Evaluate failure cases and run gate-level simulations to identify and resolve issues
Key Qualifications:
  1. MSEE or BSEE with 2+ years of digital verification experience in the industry
  2. Hands-on experience in writing testcases in Verilog and System Verilog
  3. Familiarity with code quality metrics and UVM methodology
Preferred Experience / Knowledge:
  1. High-speed digital and mixed-signal design and verification
  2. Asynchronous clock domain crossing and VCS/Verdi verification
  3. Good organization and communication skills

At Synopsys, we're driving innovation in the Era of Smart Everything. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP to help customers integrate more capabilities and meet unique performance, power, and size requirements.

We're looking for a talented digital verification engineer to join our team and contribute to the development of high-end mixed-signal designs. If you're passionate about innovation and have a strong background in digital verification, we want to hear from you.



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